1. Field of the Invention
The present disclosure generally relates to gate first technologies and herein to the selective fabrication of FuSi gates in CMOS technologies. In particular, the present disclosure relates to a method of forming a semiconductor device structure having two semiconductor devices, one with a FuSi gate and the other with a partially silicided gate, and to an according semiconductor device structure.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. Particularly, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes ranging even into the deep sub-micron regime; the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 10 nm. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs may be made much smaller than discreet circuits composed of independent circuit components. The majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors) and passive elements, such as resistors and capacitors, integrated on a semiconductor substrate with a given surface area. Typically, present-day integrated circuits involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a MOSFET is that of an electronic switching element, wherein a current through a channel region between two contact regions, referred to as source and drain, is controlled by a gate electrode to which a voltage relative to source and drain is applied. Particularly, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of a MOSFET is changed and the characteristic voltage level, usually called “threshold voltage” and in the following referred to as Vt, characterizes the switching behavior of a MOSFET. In general, Vt depends nontrivially on the transistor's properties, e.g., materials, dimensions etc., such that the implementation of a desired Vt involves plural steps of adjustment and fine-tuning during the fabrication process.
Metal gates have been realized in two general approaches: gate first and gate last. The former approach retains the order of standard polysilicon gate process flows and its main disadvantages are concerns about contamination of front end tools during processing, particularly furnaces, difficult metal etching, and the integrity of the gate stack during high temperature anneals. The gate last approach is also called a replacement gate technique, where a dummy gate is removed after all doping and high temperature processes are completed. Its main challenge is the dummy gate stack removal and replacement.
The most common digital integrated circuits built today use CMOS logic, which is fast and offers a high circuit density and a low power consumption. CMOS or “complementary symmetry metal oxide semiconductor,” as it is sometimes referred to, makes use of complementary and symmetrical pairs of P-type and N-type MOSFETs for implementing logic functions. Two important characteristics of CMOS devices are the high noise immunity and low static power consumption of a CMOS device because the series combination of complementary MOSFETs in a CMOS device draws significant power only momentarily during switching between ON- and OFF-states, since one transistor of a CMOS device is always in the OFF-state. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example, transistor-transistor logic (TTL) or NMOS logic, which normally have some standing current even when not changing state.
Full silicidation (FuSi) of polysilicon gates is used for the formation of metal gate electrodes of highly scaled CMOS transistors. A common material employed in the formation of silicide is represented by nickel, wherein nickel silicide was shown to produce different work functions, covering a large portion of silicon band gap, in relation to a dopant type and amount present in polysilicon gates.
High performance CMOS technologies generally require two separate work functions for NMOS and PMOS devices. A technique for forming tunable metal gates uses the full silicidation of doped polysilicon gates, which turns out to be relatively simple. Full silicidation is achieved when a sufficient amount of nickel is deposited on a polysilicon gate and all the polysilicon is consumed during a subsequently-performed annealing process resulting in nickel silicide. The accordingly-obtained FuSi structure has substantially different electrical characteristics from the initial polysilicon gate device.
FuSi gates in gate first technology are known to improve the DC performance of PMOS devices, according to present understanding, due to the intrinsic tensile stress of the formed silicide. However, a degradation of NMOS devices with FuSi gates in their performance by about 10% is observed and, accordingly, CMOS devices with FuSi gates show degraded performance.
In the framework of 28 nm high-k/metal gate processes and beyond (22 nm, etc.) in gate first techniques, it is, therefore, desirable to increase the performance of semiconductor device structures.